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// aiecc.py -j4 
// --sysroot=${SYSROOT} \
// --host-target=%aieHostTargetTriplet% %s \
// -I%aie_runtime_lib%/test_lib/include %extraAieCcFlags% \
// -L%aie_runtime_lib%/test_lib/lib 
// -ltest_lib %S/test.cpp \
// -o tutorial-1.exe

// REQUIRES: valid_xchess_license
// RUN: make -C %S tutorial-1.exe
// RUN: %run_on_board ./tutorial-1.exe
// RUN: make -C %S clean

// Declare this MLIR module. A block encapsulates all
// AIE tiles, buffers, and communication in an AI Engine design
module @tutorial_1 {

    ///////////// AI Engine array components and connections /////////////
    
    // Declare tile object of the AIE class located at position col 1, row 4
    %tile14 = aie.tile(1, 4)

    // Declare buffer for tile(1, 4) with symbolic name "a14" and
    // size 256 deep x int32 wide. By default, the address of
    // this buffer begins after the stack (1024 Bytes offset) and
    // all subsequent buffers are allocated one after another in memory.
    %buf = aie.buffer(%tile14) { sym_name = "a14" } : memref<256xi32>

    // Define the algorithm for the core of tile(1, 4)
    // buf[3] = 14
    %core14 = aie.core(%tile14) {
		  %val = arith.constant 14 : i32  // declare a constant (int32)
		  %idx = arith.constant 3 : index // declare a constant (index)
		  memref.store %val, %buf[%idx] : memref<256xi32> // store val in buf[3]
        aie.end
    }

    ///////////// AI Engine array components and connections /////////////
}

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%coreName = aie.core(tileName) { body }

%bufName = aie.buffer(tileName) { body } : memref<depth x data_type> 

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%lockName = aie.lock(%tileName, %lockID) { body }

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%lock14_7 = aie.lock(%tile14, 7) { sym_name = "lock14_7" }

%core14 = aie.core(%tile14) {
    aie.use_lock(%lock14_7, "Acquire", 0)
    ... core ops ...
    aie.use_lock(%lock14_7, "Release", 1)
}

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aie_libxaie_ctx_t *_xaie = mlir_aie_init_libxaie();
mlir_aie_init_device(_xaie);
mlir_aie_configure_cores(_xaie);
mlir_aie_configure_switchboxes(_xaie);
mlir_aie_configure_dmas(_xaie);
mlir_aie_initialize_locks(_xaie);

// clear local data memory for tile(1,4)
mlir_aie_clear_tile_memory(_xaie, 1, 4); 

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// 创建 buffer 并为其分配虚拟地址
ext_mem_model_t buf0, buf1;
int *mem_ptr_in = mlir_aie_mem_alloc(_xaie, buf0, 256);
int *mem_ptr_out = mlir_aie_mem_alloc(_xaie, buf1, 256);

// 设置虚拟地址指针
mlir_aie_external_set_addr_ddr_test_buffer_in(_xaie, (u64)mem_ptr_in);
mlir_aie_external_set_addr_ddr_test_buffer_out(_xaie, (u64)mem_ptr_out);
mlir_aie_configure_shimdma_70(_xaie); // configures 2 DMAs in shim DMA tile
... 
mlir_aie_sync_mem_dev(_xaie, buf0); // 写入，同步 物理 DDR 数据至 虚拟 DDR
mlir_aie_sync_mem_cpu(_xaie, buf0); // 读取，同步 虚拟 DDR 数据至 物理 DDR

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mlir_aie_start_cores(_xaie);

printf("\ntile(3,4) status\n");
mlir_aie_print_tile_status(_xaie, 3, 4);

printf("\ntile(7,0) status\n");
mlir_aie_print_shimdma_status(_xaie, 7, 0);

printf("Release ddr input/output locks(1) to enable them\n");
mlir_aie_release_ddr_test_buffer_in_lock(_xaie, 1, 0);
mlir_aie_release_ddr_test_buffer_out_lock(_xaie, 1, 0);

// Wait for shim DMA output lock
if(mlir_aie_acquire_ddr_test_buffer_out_lock(_xaie, 0, timeout) == XAIE_OK)
  printf("Acquired ddr output lock(0). Output shim dma done.\n");
else
  printf("Timed out (%d) while trying to acquire ddr output lock (0).\n", timeout);

// Sync output buffer back to DDR(Pyhsical)
mlir_aie_sync_mem_cpu(_xaie, buf1);

// Check buffer at index 5 again for expected value of 114 for tile(3,4)    
mlir_aie_check("After start cores:", mlir_aie_read_buffer_a34(_xaie, 5), 114,
               errors);
mlir_aie_check("After start cores:", mem_ptr_out[5], 114, errors);

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module @module_name {
    // target device 将影响到后续的编译和仿真
    aie.device(target_device) {
      ... 
      AIE 阵列组件、连接等声明
      ...
    }
}

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export AIE_RUNTIME_LIB=/usr/tools/mlir-air/install-aie/runtime_lib
aiecc.py --xchesscc --xbridge --aiesim ./aie.mlir -I$(AIE_RUNTIME_LIB)/x86_64/test_lib/include -L$(AIE_RUNTIME_LIB)/x86_64/test_lib/lib -ltest_lib ./test.cpp

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aiesimulator --pkg-dir=./sim --dump-vcd foo

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module @tutorial_3 {

    // 在偶数行 4，创建两个 2 tiles (col 1 and col 2)
    // 偶数行的 DM 在 Tile 内部的左侧（ DM | Core ）
    %tile14 = aie.tile(1, 4)
    %tile24 = aie.tile(2, 4)

    // 声明一个 tile(2,4) 的 buffer（256 x int32），它被 tile(1,4) 共享
    %buf = aie.buffer(%tile24) { sym_name = "a24" } : memref<256xi32>

    // 声明一个 tile(2,4) 的 lock
    %lock24_1 = aie.lock(%tile24, 1) { sym_name = "lock_a24_1" }

    // 再声明一个 tile(2,4) 的 lock， 用于通知 tile(2,4)： core14 完成
    %lock24_2 = aie.lock(%tile24, 2) { sym_name = "lock_a24_2" }

    // 定义 tile(1,4) 的 core 算法 ：为 buffer[3] 赋值 14
    // 即 buf[3] = 14
    %core14 = aie.core(%tile14) {
      // 假设 lock24_1 的初始值为 0
      aie.use_lock(%lock24_1, "Acquire", 0)

      %val = arith.constant 14 : i32
      %idx = arith.constant 3 : index
      memref.store %val, %buf[%idx] : memref<256xi32>

      aie.use_lock(%lock24_1, "Release", 1)
      aie.end
    }

    // 定义 tile(2,4) 的 core 算法 ：读取 buffer[3] 的值（tile14刚才设置的值），并将其加 100 后存入 buffer[5]
    // Define core algorithm for tile(2,4) which reads value set by tile(1,4)
    // buf[5] = buf[3] + 100
    %core24 = aie.core(%tile24) {
      // 假设 lock24_2 的初始值为 0
      aie.use_lock(%lock24_2, "Acquire", 0)
        
      // Tile(1,4) 的 core 执行完毕后，这里将会获得锁
      aie.use_lock(%lock24_1, "Acquire", 1)

      %idx1 = arith.constant 3 : index
      %d1   = memref.load %buf[%idx1] : memref<256xi32>
      %c1   = arith.constant 100 : i32
      %d2   = arith.addi %d1, %c1 : i32
      %idx2 = arith.constant 5 : index
      memref.store %d2, %buf[%idx2] : memref<256xi32>

      // 释放 lock24_2 并置为 1
      aie.use_lock(%lock24_2, "Release", 1)
      aie.end
    }
}

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aie.objectfifo @name (producerTile, {consumerTiles1, consumerTiles2, ...}, depth) : elemDatatype`

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aie.objectfifo.acquire @of (Produce|Consume, <Element Position>)
aie.objectfifo.release @of (Produce|Consume, <Element Position>)

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module @tutorial_3 {
    aie.device(xcvc1902) {
        // 在偶数行 4，创建两个 2 tiles (列 1, 列 2)
        // 偶数行的 DM 在 Tile 内部的左侧（ DM | Core ）
        %tile14 = aie.tile(1, 4)
        %tile24 = aie.tile(2, 4)

        // 声明一个 tile(2,4) 的 buffer（256 x int32），它被 tile(1,4) 共享。
        // 同时，声明一个 object FIFO 用于 tile(1,4) 和 tile(2,4) 之间的通信，
        // 其中，生产者为 tile(1,4)，消费者为 tile(2,4)，FIFO 深度为 1。
        aie.objectfifo @of (%tile14, {%tile24}, 1 : i32) : !aie.objectfifo<memref<256xi32>>

        // 原子锁，用于控制 core24 的原子性
        %lock24_2 = aie.lock(%tile24, 2) { sym_name = "lock_a24_2" }

        // 定义 tile(1,4) 的 core 算法 ：为 buffer[3] 赋值 14
        // buf[3] = 14
        %core14 = aie.core(%tile14) {
            // 创建一个 objectFIFO 的子视图，用于从 objectFIFO 中获取一个元素 1 的生产者对象，
            // 这相当于在访问 AIE 缓冲区之前获取 AIE 锁（这会根据之前的规则改变锁的值）
            %inputSubview = aie.objectfifo.acquire @of (Produce, 1) : !aieobjectfifosubview<memref<256xi32>>

            // 访问子视图的第一个元素
            %input = aie.objectfifo.subview.access %inputSubview[0] : !aieobjectfifosubview<memref<256xi32>>  -memref<256xi32>
            %val = arith.constant 14 : i32 
            %idx = arith.constant 3 : index 
            memref.store %val, %input[%idx] : memref<256xi32>

            // 释放生产者的锁
            aie.objectfifo.release @of (Produce, 1)
            aie.end
          }

        // 定义 tile(2,4) 的 core 算法 ：
        // 读取 buffer[3] 的值（tile14刚才设置的值），并将其加 100 后存入 buffer[5]
        // buf[5] = buf[3] + 100
        %core24 = aie.core(%tile24) {
            // 假设 lock24_2 的初始值为 0
            // 用于控制 core24 的原子性，请求获取 lock24_2 并置为 0
            aie.use_lock(%lock24_2, "Acquire", 0)

            %inputSubview = aie.objectfifo.acquire @of (Consume, 1) : !aie.objectfifosubview<memref<256xi32>>
            %input = aie.objectfifo.subview.access %inputSubview[0] : !aie.objectfifosubview<memref<256xi32>> -> memref<256xi32>

            %idx1 = arith.constant 3 : index
            %d1   = memref.load %input[%idx1] : memref<256xi32>
            %c1   = arith.constant 100 : i32 
            %d2   = arith.addi %d1, %c1 : i32
            %idx2 = arith.constant 5 : index
            memref.store %d2, %input[%idx2] : memref<256xi32> 

            aie.objectfifo.release @of (Consume, 1)

            // 用于控制 core24 的原子性，释放 lock24_2 并置为 1
            aie.use_lock(%lock24_2, "Release", 1)
            aie.end
        }
    }
}

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aie.objectfifo @of (%tile14, {%tile24}, 1 : i32) : !aie.objectfifo<memref<256xi32>>

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// 创建 buffer："of_buff_0"
%of_buff_0 = aie.buffer(%tile_2_4) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "of_buff_0"} : memref<256xi32> 

// 创建 lock: "of_lock_0", 并初始化为 0
%of_lock_0 = aie.lock(%tile_2_4, 0) {init = 0 : i32, sym_name = "of_lock_0"}

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%inputSubview = aie.objectfifo.acquire @of (Produce, 1) : !aie.objectfifosubview<memref<256xi32>>

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// of_lock_0 初始值之前已默认初始化为 0，这里将成功拿到锁
aie.use_lock(%of_lock_0, Acquire, 0)

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aie.objectfifo.release @of (Produce, 1)

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aie.use_lock(%of_lock_0, Release, 1)

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// ObjectFIFO
aie.objectfifo.acquire @objFifo (Produce, 1)
aie.objectfifo.release @objFifo (Produce, 1)

aie.objectfifo.acquire @objFifo (Consume, 1)
aie.objectfifo.release @objFifo (Consume, 1)

// Lowering to use_lock
aie.use_lock(%of_lock_0, "Acquire", 0)
aie.use_lock(%of_lock_0, "Release", 1)

aie.use_lock(%of_lock_0, "Acquire", 1)
aie.use_lock(%of_lock_0, "Release", 0)

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aie.flow ($sourceTile, $sourceBundle : $sourceChannel, $destTile, $destBundle : $destChannel)

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aie.flow(%tile71, "South" : 3, %tile73, "DMA"   : 0)
aie.flow(%tile73, "DMA"   : 1, %tile71, "South" : 2)

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%mem14 = aie.mem(%tile14) {
    %dma1 = aie.dma_start("MM2S", 0, ^bd0, ^end)
    ^bd0:
        aie.use_lock(%lock14_6, "Acquire", 1)
        aie.dma_bd(%buf14: memref<256xi32>, 0, 256)
        aie.use_lock(%lock14_6, "Release", 0)
        aie.next_bd ^end
    ^end:
        aie.end
}

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aie.dma_start($channelDir, $channelIndex, $dest, $chain)

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aie.dma_bd(<$buffer : type($buffer), $offset, $len>, $AB)

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%mem14 = aie.mem(%tile14) {
    %dma1 = aie.dma_start("MM2S", 0, ^bd0, ^dma2)
    ^dma2:
        %dma2 = aie.dma_start("S2MM", 0, ^bd2, ^end)
    ^bd0:
        aie.use_lock(%lock14_6, "Acquire", 0)
        aie.dma_bd(%buf14_1: memref<256xi32>, 0, 256)
        aie.use_lock(%lock14_6, "Release", 1)
        aie.next_bd ^bd1
    ^bd1:
        aie.use_lock(%lock14_7, "Acquire", 0)
        aie.dma_bd(%buf14_2: memref<256xi32>, 0, 256)
        aie.use_lock(%lock14_7, "Release", 1)
        aie.next_bd ^bd0
    ^bd2:
        aie.use_lock(%lock14_10, "Acquire", 0)
        aie.dma_bd(%buf14_3: memref<256xi32>, 0, 256)
        aie.use_lock(%lock14_10, "Release", 1)
        aie.next_bd ^bd3
    ^bd3:
        aie.use_lock(%lock14_11, "Acquire", 0)
        aie.dma_bd(%buf14_4: memref<256xi32>, 0, 256)
        aie.use_lock(%lock14_11, "Release", 1)
        aie.next_bd ^bd2
    ^end:
        aie.end
}

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aie.switchbox(%tile14) { aie.connect<"DMA": 0, "East": 1> }
aie.switchbox(%tile24) { aie.connect<"West": 1, "East": 3> }
aie.switchbox(%tile34) { aie.connect<"West": 3, "DMA": 1> }

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%shimdma70 = AIE.shim_dma(%tile70) {
    AIE.dma_start("MM2S", 0, ^bd1, ^end)
    ^bd1:
        AIE.use_lock(%lock70_in, "Acquire", 1)
        AIE.dma_bd(%external_buf : memref<256xi32>, 0, 256>, A)
        AIE.use_lock(%lock70_in, "Release", 0)
        cf.br ^end
    ^end:
        AIE.end
}

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%ext_buf70_in  = AIE.external_buffer {sym_name = "ddr_test_buffer_in"}: memref<256xi32>

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AIE.objectfifo.register_external_buffers @name (shimTile, {list of external buffers to register}) : (list of external buffer datatypes)

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int *mem_ptr_in  = mlir_aie_mem_alloc(_xaie, 0, 256);
mlir_aie_external_set_addr_ddr_test_buffer_in((u64)mem_ptr_in);
mlir_aie_configure_shimdma_70(_xaie);

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mlir_aie_acquire_<sym_name>_lock(_xaie, 1, 100);
mlir_aie_release_<sym_name>_lock(_xaie, 0, 100);

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AIE.packet_flow($packet_id) {
    AIE.packet_source<$tile, $bundle : $channel>
    AIE.packet_dest<$tile, $bundle : $channel>
}

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AIE.packet_flow(0xD) {
    AIE.packet_source<%tiler14, DMA : 0>
    AIE.packet_dest<%tile34, DMA : 1>
}

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AIE.dma_bd_packet($packet_type, $packet_id)

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^bd0:
    AIE.use_lock(%lock14_6, Acquire, 1)
    AIE.dma_bd_packet(0x4, 0xD) 
    AIE.dma_bd(%buf14 : memref<256xi32>, 0, 256)
    AIE.use_lock(%lock14_6, Release, 0)
    cf.br ^end

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AIE.flow(%tile14, DMA: 0, %tile34, DMA:0)
AIE.flow(%tile14, DMA: 0, %tile35, DMA:1)
AIE.flow(%tile14, DMA: 0, %tile36, DMA:0)

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AIEX.broadcast_packet(%tile14, DMA: 0) {
     AIEX.bp_id(0xD) {
       AIEX.bp_dest<%tile34, DMA: 1>
       AIEX.bp_dest<%tile35, DMA: 1>
     }
     ...
}

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AIEX.broadcast_packet(%tile14, Core: 0) {
     AIEX.bp_id(0xD) {
      AIEX.packet_source<%tile34, "Core" : 0>
     }
     ...
}

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AIE.packet_flow(0xD) {
  AIE.packet_source<%tile14, "Core" : 0>
  AIE.packet_dest<%tile34, "Core" : 0>
}

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AIE.rule(mask, value, amsel)

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%amsel_name = AIE.amsel<arbiter>(master select)

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aie.masterset(bundle:channel, amsel)

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%0 = AIE.tile(1,4)
%1 = AIE.switchbox(%0) {
  %amsel0 = AIE.amsel<0>(0)       # 使用仲裁器0，主选择0
  AIE.masterset(East:0, %amsel0)  # 绑定东向端口
  AIE.masterset(North:0, %amsel0) # 绑定北向端口
  AIE.packet_rules(DMA:0) {
    AIE.rule(0x1F, 0x0D, %amsel0) # 包ID=0x0D匹配到amsel0
  }
}

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%0 = AIE.tile(2,3)
%1 = AIE.switchbox(%0) {
  %amsel1 = AIE.amsel<1>(0)       # 仲裁器1，主选择0
  AIE.masterset(Core:0, %amsel1)  # 绑定到核心端口

  # West:0端口的规则
  AIE.packet_rules(West:0) {
    AIE.rule(0x1F, 0x0A, %amsel1) # 包ID=0x0A匹配到amsel1
  }

  # South:0端口的规则
  AIE.packet_rules(South:0) {
    AIE.rule(0x1F, 0x0B, %amsel1) # 包ID=0x0B匹配到amsel1
  }
}

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AIE.get_cascade()
AIE.put_cascade($cascadeValue : type($cascadeValue))

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%core13 = aie.core(%tile13) {
    aie.use_lock(%lock13_1, "Acquire", 0)

    %val = arith.constant 14 : i384
    aie.putCascade(%val : i384)
    
    func.call @extern_kernel1() : () -> ()
    
    aie.use_lock(%lock13_1, "Release", 1)
    aie.end
}{ link_with="kernel1.o" }

%core23 = aie.core(%tile23) {
    aie.use_lock(%lock13_2, "Acquire", 0)
    aie.use_lock(%lock13_1, "Acquire", 1)

    %cas1 = aie.get_cascade() : i384
    %d1   = arith.trunci %cas1 : i384 to i32
    %c1   = arith.constant 100 : i32
    %d2   = arith.addi %d1, %c1 : i32
	  %idx2 = arith.constant 5 : index
	  memref.store %d2, %buf[%idx2] : memref<256xi32>

    func.call @extern_kernel2(%buf) : (memref<256xi32>) -> ()
    aie.use_lock(%lock13_1, "Release", 0)

    aie.use_lock(%lock13_2, "Release", 1)
    aie.end
} { link_with="kernel2.o" }

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func.func private @extern_kernel_func(%b: memref<256xi32>) -> ()

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void extern_kernel_func(int32_t *restrict buf);

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%buf = aie.buffer(%tile14) { sym_name = "a14" } : memref<256xi32>

...

%core14 = AIE.core(%tile14) {
    func.call @extern_kernel_func(%buf) : (memref<256xi32>) -> ()
    AIE.end
} { link_with="kernel.o"}

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kernel.h - kernel header file
test.cc  - testbench that calls our kernel (similar to test.cpp)
test.prx - XML project file

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<project name="test" processor="me">
    <file type="c" name="kernel.cc" path=""/>
    <file type="c" name="test.cc" path=""/>
    <option id="project.name" value="test"/>
    <option id="project.type" value="exe"/>
</project>

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xchessmk -P <vitis install>/<release>/aietools/data/<aie-version>/lib test.prx

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xca_udm_dbg -P <vitis install>/<release>/aietools/data/<aie-version>/lib -t sim.tcl

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iss::create %PROCESSORNAME% iss
iss program load ./work/Release_LLVM/test.prx/test -disassemble -dwarf -nmlpath %XILINX_VITIS%/aietools/data/aie_ml/lib -extradisassembleopts +Mdec -do_not_set_entry_pc 1 -do_not_load_sp 1 -pm_check first -load_offsets {} -software_breakpoints_allowed on -hardware_breakpoints_allowed on
iss step -1
iss profile save test.prf
iss close
exit

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aiecc.py -j4 --sysroot=<platform sysroot> -host-target=aarch64-linux-gnu aie.mlir -I<runtime_lib> <runtime lib>/test_library.cpp ./test.cpp -o test.exe

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aie-opt \
--lower-affine \
--aie-canonicalize-device \
--aie-assign-lock-ids \
--aie-register-objectFifos \
--aie-objectFifo-stateful-transform \
--aie-lower-broadcast-packet \
--aie-lower-multicast \
--aie-assign-buffer-addresses \
--convert-scf-to-cf \
aie.mlir -o input_with_addresses.mlir

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aie-translate --aie-generate-corelist input_with_addresses.mlir

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aie-opt \
--aie-localize-locks \
--aie-standard-lowering \
--aie-normalize-address-spaces \
--canonicalize \
--cse \
--convert-vector-to-llvm \
--expand-strided-metadata \
--lower-affine \
--convert-arith-to-llvm \
--convert-memref-to-llvm \
--convert-func-to-llvm=use-bare-ptr-memref-call-conv \
--convert-cf-to-llvm \
--canonicalize --cse \
input_with_addresses.mlir -o input_opt_with_addresses.mlir

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aie-translate \
--opaque-pointers=0 \
--mlir-to-llvmir \
input_opt_with_addreses.mlir -o input.ll

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xchesscc_wrapper -c -d -f +P 4 file_llvmir_hacked -o input.o

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aie-opt \
--aie-create-pathfinder-flows \
--aie-lower-broadcast-packet \
--aie-lower-multicast \
input_with_addresses.mlir -o input_physical.mlir

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aie-translate --aie-generate-xaie --xaie-target=v2 input_physical.mlir -o aie_inc.cpp

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aie-opt \
--aie-localize-locks \
--aie-standard-lowering=tilecol=COL tilerow=ROW % core[0:2] \
input_with_addresses.mlir -o core_*.mlir

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aie-opt \
-aie-normalize-address-spaces \
--canonicalize \
--cse \
--convert-vector-to-llvm \
--expand-strided-metadata \
--lower-affine \
--convert-arith-to-llvm \
--convert-memref-to-llvm \
--convert-func-to-llvm=use-bare-ptr-memref-call-conv \
--convert-cf-to-llvm \
--canonicalize \
--cse \
core*.mlir -o opt.mlir

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aie-translate input_with_addresses.mlir --aie-generate-bcf --tilecol=COL --tilerow=ROW -o core*.bcf

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aie-translate input_with_addresses.mlir --aie-generate-ldscript --tilecol=COL --tilerow=ROW -o core*.ld.script

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xchesscc_wrapper -d -f core*.o link_with_obj +l core*bcf -o core*elf